These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of input logic ensures that all outputs remain off for all invalid (10± 15) input conditions.
1. Diode clamped inputs 2. Also for applications as 4-line-to-16-line decoders; 3-line-to-8-line decoders 3. All outputs are high for invalid input conditions
Acquired by Texas Instruments on September 23rd, 2011.
Other data sheets within the file : 54LS42, 54LS42DMQB, 54LS42FMQB, DM54LS42