25P05 PDF Datasheet – 512 Kbit Flash Memory (M25P05)

Part Number : 25P05, M25P05

Function : 512 Kbit Flash Memory

Package : SO 8 Pin Type

Manufactures : STMicroelectronics

Images :

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25P05 image

Description :

The M25P05 is a 512 Kbit (64K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 128 bytes at a time, using the Page Program instruction. The memory is organized as 2 sectors, each containing 256 pages. Each page is 128 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 65536 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

Features :

1. 512 Kbit of Flash Memory
2. Page Program (up to 128 Bytes) in 3 ms (typical)
3. Sector Erase (256 Kbit) in 1 s (typical)
4. Bulk Erase (512 Kbit) in 2 s (typical)
5. 2.7 V to 3.6 V Single Supply Voltage
6. SPI Bus Compatible Serial Interface
7. 20 MHz Clock Rate (maximum)
8. Deep Power-down Mode 1 µA (typical)
9. Electronic Signature

Figure 2. Logic Diagram VCC Figure 3. SO Connections M25P05 S Q W VSS 1 2 3 4 8 7 6 5 AI04038 VCC HOLD C D D C S W HOLD M25P05 Q VSS AI04037 Table 1. Signal Names C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground S W HOLD VCC VSS 2/32 M25P05 SIGNAL Description Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the devic […]

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25P05 Datasheet