25P40 Datasheet – 4Mb, Flash Memory (M25P40)

Part Number : 25P40

Function : M25P40

Manufactures : ST Microelectronics

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Description :

M25P40 4 Mbit, Low Voltage, Serial Flash Memory With 25 MHz SPI Bus Interface Features SUMMARY s 4 Mbit of Flash Memory s Figure 1. Packages Page Program (up to 256 Bytes) in 1.5ms (typical) Sector Erase (512 Kbit) in 2 s (typical) (4 Mbit) in 5 s (typical) 2.7 V to 3.6 V Single Supply Voltage SPI Bus Compatible Serial Interface 25 MHz Clock Rate (maximum) Deep Power-down Mode 1 µA (typical) Electronic Signature (12h) More than 100,000 Erase/Program Cycles per Sector More than 20 Year Data Retention s s Bulk Erase s s s s s s 8 1 SO8 (MN) 150 mil width s VFQFPN8 (MP) (MLP8) June 2003 1/35 M25P40 SUMMARY Description The M25P40 is a 4 Mbit (512K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Figure 2. Logic Diagram VCC Figure 3. SO and VFQFPN Connections M25P40 S Q W VSS 1 2 3 4 8 7 6 5 AI04091B VCC HOLD C D D C S W HOLD M25P40 Q Note: 1. See page 31 (onwards) for package dimensions, and how to identify pin-1. VSS AI04090 Table 1. Signal Names C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground S W HOLD VCC VSS 2/35 M25P40 SIGNAL Description Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data I […]

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25P40 Datasheet

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