Part Number : 7410
Function : Triple 3-input NAND gate
Manufactures : Philips
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Description :
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT10 Triple 3-input NAND gate Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Triple 3-input NAND gate Product specification 74HC/HCT10 FEATURES • Output capability: standard • ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL PARAMETER CONDITIONS tPHL/ tPLH CI CPD propagation delay nA, nB, nC to nY input capacitance power dissipation capacitance per gate CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fO) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V. TYPICAL HC 9 3.5 12 HCT 11 3.5 14 UNIT ns pF pF ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 Philips Semiconductors Triple 3-input NAND gate PIN DESCRIPTION PIN NO. 1, 3, 9 2, 4, 10 13, 5, 11 12, 6, 8 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND FUNCTION data inputs data inputs data inputs data outputs ground (0 V) positive supply voltage Product specification 74HC/HCT10 Fig.1 Pin configuration. Fig.4 Functional diagram. December 1990 Fig.2 Logic symbol. Fig.3 IEC logic symbol. Fig.5 Logic diagram (one gate). FUNCTION TABLE INPUTS nA nB nC LLL L LH LHL L HH OUTPUT nY H H H H HL L HLH HH L HHH H H H L Notes 1. H = HIGH voltage level L = LOW voltage level 3 Philips Semiconductors Triple 3-input NAND gate Product specification 74HC/HCT10 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) SYMBOL PARAMETER 74HC +25 −40 to + 85 min. typ. max. min. max. tPHL/ tPLH propagation delay nA, nB, nC to nY tTHL/ tTLH output transition time 30 95 11 19 9 16 19 75 7 15 6 13 120 24 20 95 19 16 UNIT −40 to + 125 min. max. 145 29 ns 25 110 22 ns 19 TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 Fig.6 6.0 2.0 4.5 Fig.6 6.0 December 1990 4 Philips Semiconductors Triple 3-input NAND gate Product specification 74HC/HCT10 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specific […]
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