74LS138 Datasheet – Decoder / Demultiplexer

Part Number : 74LS138, HD74LS138P

Function : 3-LINE TO 8-LINE DECODER / DEMULTIPLEXER

Package : DIP 16 Pin type

Manufacturers : Hitachi Semiconductor, Texas Instruments, Motorola

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74LS138 Decoder Demultiplexer

 

Description

These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The LSTTL/MSI SN74LS138 is a high speed 1-of-8 Decoder/Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.

Pinouts

74LS138 datasheet pinout

Features

1. Designed specifically for high speed : Memory decoders Data transmission systems
2. DM74LS138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception
3. DM74LS139 contains two fully independent 2-to-4-line decoders/demultiplexers
4. Schottky clamped for high performance
5. Typical propagation delay (3 levels of logic)
DM74LS138 21 ns
DM74LS139 21 ns
6. Typical power dissipation
DM74LS138 32 mW
DM74LS139 34 mW

 

74LS138 Datasheet PDF Download

SN74LS138N pdf

Other data sheets within the file : DM74LS138, DM74LS139