74LS569 Datasheet – 4-BIT UP/DOWN COUNTER – Motorola

Part Number : 74LS569


PackageĀ : DIP, SOP 8 Pin type

Manufacturers : Motorola

ImageĀ :

74LS569 datasheet

Description :

The 74LS569 is designed as programmable up/down BCD and Binary counters respectively. These devices have 3-state outputs for use in bus organized systems. With the exception of output enable (OE)and asynchronous clear (ACLR), all functions occur on the positive edge of the clock pulse (CP).
When the LOAD input is LOW, the outputs will be programmed by the parallel data inputs (A, B, C, D) on the next clock edge. Enabling of the counters occurs only when CEP and CET are LOW and LOAD is HIGH. Direction of the count is controlled by the up-down input (U/D), HIGH counts up and LOW counts down. High-speed counting and cascading is implemented by internal look-ahead carry logic and an active LOW ripple carry output (RCO). On the LS569A, the RCO is LOW at binary 15 during up-count and during down-count it is also LOW at binary 0. During normal cascading operation RCO connected to the succeeding block at CET is the only requisite. When counting and when RCO is LOW, the clocked carry output (CCO) provides a HIGH-LOW-HIGH pulse for a duration equal to the LOW time of the clock pulse. Two active LOW reset lines are provided, a master reset asynchronous clear (ACLR) and a synchronous clear (SCLR). When in a HIGH state, the output control (OE) input forces the counter output into a HIGH impedance state and when LOW, the counter outputs are enabled.






74LS569 Datasheet PDF


Other data sheets within the file : SN74LS569N, SN74LS569DW, 74569