Part Number : 8088


Manufactures : Intel Corporation

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8088 image

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Description :

8088 8-BIT HMOS MICROPROCESSOR 8088 8088-2 Y Y Y 8-Bit Data Bus Interface 16-Bit Internal Architecture Direct Addressing Capability to 1 Mbyte of Memory Direct Software Compatibility with 8086 CPU 14-Word by 16-Bit Register Set with Symmetrical Operations 24 Operand Addressing Modes Y Y Byte Word and Block Operations 8-Bit and 16-Bit Signed and Unsigned Arithmetic in Binary or Decimal Including Multiply and Divide Two Clock Rates 5 MHz for 8088 8 MHz for 8088-2 Available in EXPRESS Standard Temperature Range Extended Temperature Range Y Y Y Y Y The Intel 8088 is a high performance microprocessor implemented in N-channel depletion load silicon gate technology (HMOS-II) and packaged in a 40-pin CERDIP package The processor has attributes of both 8and 16-bit microprocessors It is directly compatible with 8086 software and 8080 8085 hardware and peripherals 231456 – 2 231456 – 1 Figure 2 8088 Pin Configuration Figure 1 8088 CPU Functional Block Diagram August 1990 Order Number 231456-006 8088 Table 1 Pin Description The following pin function descriptions are for 8088 systems in either minimum or maximum mode The ‘‘local bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8088 (without regard to additional bus buffers) Symbol Pin No Type Name and Function AD7–AD0 9–16 I O ADDRESS DATA BUS These lines constitute the time multiplexed memory IO address (T1) and data (T2 T3 Tw T4) bus These lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ‘‘hold acknowledge’’ A15–A8 2–8 39 O ADDRESS BUS These lines provide address bits 8 through 15 for the entire bus cycle (T1 – T4) These lines do not have to be latched by ALE to remain valid A15 – A8 are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ‘‘hold acknowledge’’ A19 S6 A18 S5 35–38 O ADDRESS STATUS During T1 these are the four most significant A17 S4 A16 S3 address lines for memory operations During I O operations these lines are LOW During memory and I O operations status information is available on these lines during T2 T3 Tw and T4 S6 is always low The status of the interrupt enable flag bit (S5) is updated at the beginning of each clock cycle S4 and S3 are encoded as shown This information indicates which segment register is presently being used for data accessing These lines float to 3-state OFF during local bus ‘‘hold acknowledge’’ S4 S3 Characteristics 0 (LOW) 0 Alternate Data 0 1 Stack 1 (HIGH) 0 Code or None 1 1 Data S6 is 0 (LOW) RD 32 O READ Read strobe indicates that the processor is performing a memory or I O read cycle depending on the state of the IO M pin or S2 This signal is used to read devices which reside on the 8088 local bus RD is active LOW during T2 T3 and Tw of any read cycle and is guaranteed to remain HIGH in T2 until the 8088 local bus has floated This signal floats to 3-state OFF in ‘‘hold acknowledge’’ […]

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8088 Datasheet

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