A3S56D40FTP – 256M Double Data Rate Synchronous DRAM

Part Number : A3S56D40FTP

Function : 256M Double Data Rate Synchronous DRAM

Manufactures : Zentel

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Description :

A3S56D30FTP A3S56D40FTP 256M Double Data Rate Synchronous DRAM 256Mb DDR SDRAM Specification A3S56D30FTP A3S56D40FTP Zentel Electronics Corp. Revision 1.3 Apr., 2010 A3S56D30FTP A3S56D40FTP 256M Double Data Rate Synchronous DRAM DESCRIPTION A3S56D30FTP is a 4-bank x 8,388,608-word x 8bit, A3S56D40FTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK. The A3S56D30/40FTP achieves very high speed clock rate up to 250 MHz . FEATURES – Vdd=VddQ=2.5V+0.2V (-4, -5E, -5) – Double data rate architecture ; two data transfers per clock cycle. – Bidirectional , data strobe (DQS) is transmitted/received with data – Differential clock input (CLK and /CLK) – DLL aligns DQ and DQS transitions with CLK transitions edges of DQS – Commands entered on each positive CLK edge ; – Data and data mask referenced to both edges of DQS – 4 bank operation controlled by BA0 , BA1 (Bank Address) – /CAS latency – 2.0 / 2.5 / 3.0 / 4.0 (programmable) ; Burst length – 2 / 4 / 8 (programmable) Burst type – Sequential / Interleave (programmable) – Auto Precharge / All Bank Precharge controlled by A10 – Support concurrent Auto Precharge – 8192 refresh cycles / 64ms (4 banks concurrent refresh) – Auto Refresh and Self Refresh – Row address A0-12 / Column address A0-9(x8) /A0-8(x16) – SSTL_2 Interface – Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch Zentel Electronics Corporation reserve the right to change products or specification without notice. Revision 1.3 Page 1 / 39 Apr., 2010 A3S56D30FTP A3S56D40FTP 256M Double Data Rate Synchronous DRAM Pin Assignment (Top View) 66-pin TSOP x8 x16 Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC NC VddQ NC NC Vdd NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 Vdd Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 NC VddQ LDQS NC Vdd NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66pin TSOP(II) 400mil width x 875mil length 0.65mm Lead Pitch Row A0-12 Column A0-9 (x8) A0-8 (x16) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 CLK, /CLK CKE /CS /RAS /CAS /WE DQ0-15 DQ0-7 UDM, LDM DM UDQS, LDQS DQS : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O (x16) : Data I/O (x8) : Write Mask (x16) : Write Mask (x8) : Data Strobe (x16) : Data Strobe (x8) A0-12 BA0,1 Vdd VddQ Vss VssQ VREF Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 NC VssQ UDQS NC VREF Vss UDM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 Vss Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC NC VssQ DQS NC VREF Vss DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A […]

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A3S56D40FTP Datasheet


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