AR9344-DC3A – Highly-Integrated and Feature-Rich IEEE 802.11n 2×2 2.4/5 GHz Premium SoC

Part Number : AR9344-DC3A

Function : Highly-Integrated and Feature-Rich IEEE 802.11n 2×2 2.4/5 GHz Premium SoC

Manufactures : Atheros

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Description :

Data Sheet PRELIMINARY December 2010 AR9344-DC3A Highly-Integrated and Feature-Rich IEEE 802.11n 2×2 2.4/5 GHz Premium SoC for Advanced WLAN Platforms General Description The Atheros AR9344-DC3A is a highly integrated and feature-rich IEEE 802.11n 2×2 2.4/5 GHz Systemon-a-Chip (SoC) for advanced WLAN platforms. It includes a MIPS 74Kc processor, PCI Express 1.1 Root Complex and Endpoint interfaces, five port IEEE 802.3 Fast Ethernet Switch with MAC/ PHY, one MII/RMII/RGMII interface, one USB 2.0 MAC/PHY, and external memory interface for serial Flash, SDRAM, DDR1 or DDR2, I2S/ SPDIF-Out audio interface, SLIC VOIP/PCM interface, two UARTs, and GPIOs that can be used for LED controls or other general purpose interface configurations. The AR9344-DC3A supports 802.11n operations up to 144 Mbps for 20 MHz and 300 Mbps for 40 MHz respectively, and 802.11a/b/g data rates. Additional features include Maximal Likelihood (ML) decoding, Low-Density Parity Check (LDPC), Maximal Ratio Combining (MRC), Tx Beamforming (TxBF), and On-Chip One-Time Programmable (OTP) memory. The AR9344-DC3A PCIE Root Complex interface can be used to connect to another Atheros single-chip MAC/BB/radio for dual concurrent WLAN applications. The AR9344-DC3A supports booting from either NOR or NAND flash. If NOR flash is used as boot codestore, an additional NAND flash device can still be connected, for end-user multimedia storage and other applications. When connecting the AR9344-DC3A to an external host through the PCIE Endpoint interface, or the USB Device interface, the AR9344-DC3A can off load the host CPU from computation- intensive functions, allowing it to focus on its dedicated tasks. Features ■ 74Kc MIPS processor with 64 KB I-Cache and ■ External 16- or 32-bit DDR1, DDR2 operating 32 KB D-Cache, operating at up to 533 MHz at up to 200 MHz (400 M transfers/sec), or 16bit SDRAM memory interface operating at up to 200 MHz NAND and SPI NOR Flash memory support 10/100 Ethernet Switch with five IEEE 802.3 Ethernet LAN ports MII/RMII/RGMII interface 802.3az Energy Efficient Ethernet compliant Hardware-based NAT & ACL accelerators for Ethernet interface Both PCI Express 1.1 Root Complex and Endpoint interfaces supported simultaneously One USB 2.0 controller with built-in MAC/ PHY supports Host or Device mode Boot from external CPU via PCIE, USB, xMII, eliminating need for external flash I2S/SPDIF-out audio interface SLIC for VOIP/PCM One low-speed UART (115 Kbps), one highspeed UART (3 Mbps), and multiple GPIO pins for general purpose I/O Fully integrated RF Front-End including PAs and LNAs Optional external LNA/PA 25 MHz or 40 MHz reference clock input 1.2 V switching regulator Advanced power management with dynamic clock switching for ultra-low power modes 409-pin BGA package AR9344-DC3A System Block Diagram © 2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless […]

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AR9344-DC3A Datasheet


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