Part Number : H9TQ17ABJTMCUR
Function : 16GB eNAND (x8) / LPDDR3 16Gb(x32)
Manufactures : Hynix Semiconductor
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Description :
CI-MCP Specification 16GB eNAND (x8) + 16Gb LPDDR3 (x32) This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.1 / Mar. 2014 1 Preliminary H9TQ17ABJTMCUR series 16GB eNAND (x8) / LPDDR3 16Gb(x32) Document Title CI-MCP 16GB eNAND(x8) Flash / 16Gb (x32) LPDDR3 Revision History Revision No. 0.1 – Initial Draft History Draft Date Mar. 2014 Remark Preliminary Rev 0.1 / Mar. 2014 2 Preliminary H9TQ17ABJTMCUR series 16GB eNAND (x8) / LPDDR3 16Gb(x32) FEATURES [ CI-MCP ] ● Operation Temperature – (-25)oC ~ 85oC ● Package – 221-ball FBGA – 11.5×13.0mm2, 1.0t, 0.5mm pitch – Lead & Halogen Free [ e-NAND ] [ LPDDR3 ] • eMMC5.0 compatible (Backward compatible to eMMC4.5) • Bus mode – Data bus width : 1 bit(default), 4 bits, 8 bits – Data transfer rate: up to 400MB/s (HS400) – MMC I/F Clock frequency : 0~200MHz – MMC I/F Boot frequency : 0~52MHz • Operating voltage range – Vcc (NAND) : 2.7 – 3.6V – Vccq (Controller) : 1.7 – 1.95V / 2.7 – 3.6V • Temperature – Operation (-25℃ ~ +85℃) – Storage without operation (-40℃ ~ +85℃) • Others – This product is compliance with the RoHS directive • Supported features – HS400, HS200 – HPI, BKOPS – Packed CMD, Cache – Partitioning, RPMB – Discard, Trim, Erase, Sanitize – Write protect, Lock / Unlock – PON, Sleep / Awake – Reliable write – Boot feature, Boot partition – HW / SW Reset – Field firmware update – Configurable driver strength – Health(Smart) report – Production state awareness – Secure removal type VDD1 = 1.8V (1.7V to 1.95V) VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30) HSUL_12 interface (High Speed Unterminated Logic 1.2V) Double data rate architecture for command, address and data Bus; – all control and address except CS_n, CKE latched at both rising and falling edge of the clock – CS_n, CKE latched at rising edge of the clock – two data accesses per clock cycle Differential clock inputs (CK_t, CK_c) Bi-directional differential data strobe (DQS_t, DQS_c) – Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c) – Data outputs aligned to the edge of the data strobe (DQS_t, DQS_c) when READ operation – Data inputs aligned to the center of the data strobe (DQS_t, DQS_c) when WRITE operation DM masks write data at the both rising and falling edge of the data strobe Programmable RL (Read Latency) and WL (Write Latency) Programmable burst length: 8 Auto refresh and self refresh supported All bank auto refresh and per bank auto refresh supported Auto TCSR (Temperature Compensated Self Refresh) PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask DS (Drive Strength) DPD (Deep Power Down) ZQ (Calibration) ODT (On Die Termination) Rev 0.1 / Mar. 2014 3 Functional Block Diagram e-NAND Block Diagram Prelimin […]
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