HD74LS00 – Quadruple 2-Input NAND Gates

Part Number : HD74LS00

Function : Quadruple 2-Input NAND Gates

Manufactures : Hitachi Semiconductor

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Description :

HD74LS00 Quadruple 2-Input NAND Gates Features Ordering Information Part Name Package Type Package Code Package (Previous Code) Abbreviation HD74LS00P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS00FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP HD74LS00RPEL SOP-14 pin (JEDEC) PRSP0014DE-A (FP-14DNV) RP Note: Please consult the sales office for the above package availability. REJ03D0387–0200 Rev.2.00 Feb.18.2005 Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) EL (2,500 pcs/reel) Pin Arrangement 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 (Top view) 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y Rev.2.00, Feb.18.2005, page 1 of 5 HD74LS00 Circuit Schematic (1/4) Inputs A B 8k 20k VCC 75 4.5k 1.5k 3k Output Y GND Absolute Maximum Ratings Item Supply voltage Symbol VCC Note Ratings 7 Input voltage VIN 7 Power dissipation PT 400 Storage temperature Tstg –65 to +150 Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Symbol VCC IOH IOL Topr Min 4.75 — — –20 Typ 5.00 — — 25 Max 5.25 –400 8 75 Unit V V mW C Unit V A mA C Rev.2.00, Feb.18.2005, page 2 of 5 HD74LS00 Electrical Characteristics Item Input voltage Output voltage Symbol VIH VIL VOH VOL IIH Input current IIL II Short-circuit output current IOS Supply current ICCH ICCL Input clamp voltage VIK Note: – VCC = 5 V, Ta = 25 C min. 2.0 — 2.7 — — — — — –20 — — — typ.- — — — — — — — — — 0.8 2.4 — max. — 0.8 — 0.5 0.4 20 –0.4 0.1 –100 1.6 4.4 –1.5 Unit V V V V A mA mA mA mA mA V (Ta = –20 to +75 °C) Condition VCC = 4.75 V, VIL = 0.8 V, IOH = –400 A IOL = 8 mA IOL = 4 mA VCC = 4.75 V, VIH = 2 V VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Symbol min. typ. max. Unit Condition Propagation delay time tPLH tPHL — — 9 10 15 15 ns ns CL = 15 pF, RL = 2 k Note: Refer to Test Circuit and Waveform of the Common Item TTL Common Matter (Document No.: REJ27D00050100). Rev.2.00, Feb.18.2005, page 3 of 5 HD74LS00 Package Dimensins JEITA Package Code P -D IP1 4 -6.3 x 19 .2-2 .5 4 RENESAS Code P RD P0 0 14 A B-B D 14 Previous Code DP-14AV 8 M AS S[T y p.] 0.97g 1 Z 7 b3 e bp JEITA Package Code P -S OP 1 4- 5 .5x 1 0.0 6- 1 .27 RENESAS Code P RS P0 0 14 D F-B Previous Code F P-1 4D AV *1 D 14 8 Index mark 1 Z e 7 *3 b p xM y MA S S[T yp .] 0.23g F c e1 ( Ni/Pd/Au plating ) Reference Symbol e1 D E A A1 bp b3 c e Z L Dimension in Millimeters Min Nom Max 7.62 19.2 20.32 6.3 7.4 5.06 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 2.39 2.54 NOTE) 1. DIMENSIONS”*1 (Nom)”AND”*2″ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION”*3″DOES NOT INCLUDE TRIM OFFSET. […]

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HD74LS00 Datasheet


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