Part Number: IT8721F-DX
Function: Super I/O (Input/Output) Chip
Package: QFP 128 Pin Type
Manufacturer: ITE, ELITEGROUP COMPUTER SYSTEMS
The IT8721F-DX is a highly integrated Super I/O using the Low Pin Count Interface. It provides the most commonly used legacy Super I/O functionality plus the latest Environment Control initiatives, including H/W Monitor and Fan Speed Controller. The device’s LPC interface complies with Intel “LPC Interface Specification Rev. 1.1”. The IT8728F is ACPI & LANDesk compliant.
ELITEGROUP COMPUTER SYSTEMS CO., LTD. Date: 3/10/2011 Page: 3 1. Technical Issue Survey Priority/Schedule Priority Target Schedule □ Urgent 2010/1/25 ■ High □ Low Note: A). Urgent: To finish the survey and solution implementation within one or two days. B). High: To finish the survey and solution implementation within one week. C). Low: To finish the survey within two or three weeks for reference. 2. Technical Issue Description System will power shutdown when resume from S3 state, refer to below measurement of comparison with the perspective signals PCH circuit core 1.05V and SIO PWROK in failure state: 1)PCH core 1.05V circuit: 2)SIO PWROK connect to pin 32 PWRGD1_30ms : Doc.: ECS Technical Issue Survey Form V.A Free Datasheet http:/// ELITEGROUP COMPUTER SYSTEMS CO., LTD. Date: 3/10/2011
Page: 4 3)Below waveform demonstrate fail state of PWROK is ready 28 ms after PCH core 1.05V active: Below timing diagram of IBX EDS demonstrate power sequence from S3 to S0, the relation between PCH core 1.05V and PWROK are described when PCH core 1.05V is ready minima 10ms after PWROK active. Doc.: ECS Technical Issue Survey Form V.A Free Datasheet http:/// ELITEGROUP COMPUTER SYSTEMS CO., LTD. Date: 3/10/2011 Page: 5 Root cause : Power sequence between PCH core 1.05V and PWROK resume from S3 to S0 are failure. Solution : PWROK output signal changed from pin 32 PWRGD1_30ms to pin 78 PWRGD3_150ms to meet the correctly power sequence of PCH core 1.05V stable to PWROK active specification , and configure SIO PWRGD3_150ms time t5 to 135ms from register address 2A , Bit 0=1, refer to below picture: 1)SIO connect to pin78 : 2)SIO register set address 2A,Bit 0=1 : 3)Correctly waveform with implementation of solution , PCH core 1.05V stable 106 ms to PWROK active : Doc.: ECS Technical Issue Survey Form V.A Free Datasheet ELITEGROUP COMPUTER SYSTEMS CO., LTD. Date: 3/10/2011 Page: 6 If your design is similar was described above , please fill the survey form : 1-PWROK connect to PWRGD3_150ms pin 78 of SIO IT8721F-BX/DX. 2-SIO IT8721F-BX/DX pin PWRGD3_150ms delay 135 ms configure register address 2A , Bit 0=1. 3-Make sure your power sequence resume S3 to S0 of PCH core 1.05V and PWROK are correctly. 3. Technical Issue Response/Confirmation by Project Team Project Project Name List Team/Owner RD1 OK H/W 1: Eric NG H55H-LAIO : SI […]