Part Number : KMN9W000RM-B205
Function : 2GB eMMC + 2Gb LPDDR2 S4 SDRAM
Manufactures : Samsung
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Rev. 1.0, Apr. 2013 KMN9W000RM-B205 0.1, Oct. 2011 MCP Specification 2GB e·MMC + 2Gb LPDDR2 S4 SDRAM datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an “AS IS” basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2013 Samsung Electronics Co., Ltd. All rights reserved. -1- KMN9W000RM-B205 datasheet Revision History Revision No. 0.0 1.0 History Initial issue. – 2GB e·MMC A-die_ Ver 0.5 – 2Gb LPDDR2 S4 SDRAM D-die_ Ver 1.4 <2GB e·MMC A-die>_Ver 0.6 1. Entering Time for APS Mode is changed to 6ms in Table 25 . – Final datasheet. Draft Date Mar. 25, 2013 Apr. 12, 2013 Rev. 1.0 MCP Memory Remark Preliminary Editor K.N.Kang Final K.N.Kang -2- KMN9W000RM-B205 datasheet Rev. 1.0 MCP Memory 1. FEATURES Operating Temperature : -25C ~ 85C Package : 162ball FBGA Type – 11.5 x 13 x 1.0mmt, 0.5mm pitch embedded MultiMediaCard System Specification Ver. 4.41 compatible. Detail description is referenced by JEDEC Standard SAMSUNG e·MMC supports below special features which are defined in JEDEC – High Priority Interrupt scheme is supported – Background operation is supported. Full backward compatibility with previous MultiMediaCard system specification (1bit data bus, multi-e·MMC systems) Data bus sidth :1bit(Default), 4bit and 8bit MMC I/F Clock Frequency : 0 ~ 52MHz MMC I/F Boot Frequency : 0 ~ 52MHz Dual Data Rate mode is supported Power : Interface power → VDD = VCCQm (1.70V ~ 1.95V or 2.7V ~ 3.6V) , Memory power → VDDF = VCCm (2.7V ~ 3.6V) • Double-data rate architecture; two data transfers per clock cycle • Bidirectional data strobes (DQS, DQS), These are transmitted/ received with data to be used in capturing data at the receiver • Differential clock inputs (CK and CK) • Differential data strobes (DQS and DQS) • Commands & addresses entered on both positive and negative CK edges; data and data mask referenced to both edges of DQS • 8 internal ban […]
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