MSP4440K – Multistandard Sound Processor

Part Number : MSP4440K

Function : Multistandard Sound Processor

Manufactures : Micronas Semiconductor

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Description :

PRELIMINARY DATA SHEET MICRONAS MSP 44x0G Multistandard Sound Processor Family Edition May 16, 2001 6251-533-1PD MICRONAS MSP 44x0G Contents Page 6 7 8 8 10 11 11 11 11 12 12 12 12 14 14 14 14 14 14 14 15 15 15 15 15 15 16 16 16 16 16 16 17 17 17 18 18 18 19 19 20 20 20 20 20 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.5.5. 2.5.5.1. 2.5.5.2. 2.5.5.3. 2.6. 2.6.1. 2.6.2. 2.7. 2.7.1. 2.7.2. 2.7.2.1. 2.7.2.2. 2.7.3. 2.8. 2.9. 2.10. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.4.1. 3.1.4.2. 3.1.4.3. 3.1.4.4. Title PRELIMINARY DATA SHEET Introduction Features of the MSP 44x0G Family and Differences to MSPD MSP 44x0G Version List MSP 44x0G Versions and their Application Fields Functional Description Architecture of the MSP 44x0G Family Sound IF Processing Analog Sound IF Input Demodulator: Standards and Features Preprocessing of Demodulator Signals Automatic Sound Select Manual Mode Preprocessing for SCART and I2S Input Signals Source Selection and Output Channel Matrix Audio Baseband Processing Automatic Volume Correction (AVC) Loudspeaker and Headphone Outputs Subwoofer Output Quasi-Peak Detector Micronas Dynamic Bass (MDB) Dynamic Amplification Adding Harmonics MDB Parameters SCART Signal Routing SCART DSP In and SCART Out Select Stand-by Mode I2S Bus Interfaces Two-Channel I2S-Input Multichannel I2S-Input Using I2S_DA_IN3 Using I2S_DA_IN1/2/3 Two or Eight-Channel I2S-Output ADR Bus Interface Digital Control I/O Pins and Status Change Indication Clock PLL Oscillator and Crystal Specifications Control Interface I2C Bus Interface Internal Hardware Error Handling Description of CONTROL Register Protocol Description Proposals for General MSP 44x0G I2C Telegrams Symbols Write Telegrams Read Telegrams Examples 2 Micronas PRELIMINARY DATA SHEET MSP 44x0G Contents, continued Page 20 20 20 24 25 25 25 27 29 30 43 44 44 44 44 44 45 45 45 45 47 47 48 51 54 56 58 58 59 59 59 60 61 62 62 63 64 65 66 69 70 70 71 74 Section 3.2. 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. 3.3.2.7. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 3.5.7. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.2.4. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 4.6.3.9. 4.6.3.10. Title Start-Up Sequence: Power-Up and I2C-Controlling MSP 44x0G Programming Interface User Registers Overview Description of User Registers STANDARD SELECT Register Refresh of STANDARD SELECT Register STANDARD RESULT Register Write Registers on I2C Subaddress 10hex Read Registers on I2C Subaddress 11hex Write Registers on I2C Subaddress 12hex Read Registers on I2C Subaddress 13hex Programming Tips Examples of Minimum Initialization Codes B/G-FM (A2 or NICAM) BTSC-Stereo BTSC-SAP with SAP at Loudspeaker Channel FM-Stereo Radio Automatic Standard Detection SCART1 Input to Loudspeaker in […]

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MSP4440K Datasheet


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