PH6030L – N-channel TrenchMOS logic level FET

Part Number : PH6030L

Function : N-channel TrenchMOS logic level FET

Manufactures : NXP

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Description :

PH6030L N-channel TrenchMOS logic level FET Rev. 01 — 29 July 2008 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features and benefits „ Lead-free package „ Logic level compatibile „ Optimized for use in DC-to-DC converters „ Very low switching and conduction losses 1.3 Applications „ DC-to-DC convertors „ Notebook computers „ Switched-mode power supplies „ Voltage regulators 1.4 Quick reference data Table 1. Quick reference Symbol VDS ID Parameter drain-source voltage drain current Conditions Tj ≥ 25 °C; Tj ≤ 150 °C Tmb = 25 °C; VGS = 10 V; see Figure 1; see Figure 3 Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID = 25 A; VDS = 12 V; see Figure 11; see Figure 12 Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 9; see Figure 10 Min Typ Max Unit – – 30 V – – 76.7 A – 3.1 – nC – 4.7 6 mΩ NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description 1, 2, 3 S source 4G gate mb D mounting base; connected to drain 3. Ordering information Simplified outline mb 1234 SOT669 (LFPAK) Graphic symbol D G mbb076 S Table 3. Ordering information Type number Package Name PH6030L LFPAK 4. Limiting values Description Version Plastic single-ended surface-mounted package (LFPAK); SOT669 4 leads Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDS VDGR VGS ID Parameter drain-source voltage drain-gate voltage gate-source voltage drain current IDM peak drain current Conditions Tj ≥ 25 °C; Tj ≤ 150 °C 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ VGS = 10 V; Tmb = 100 °C; see Figure 1 VGS = 10 V; Tmb = 25 °C; see Figure 1; see Figure 3 tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 Ptot total power dissipation Tstg storage temperature Tj junction temperature Source-drain diode Tmb = 25 °C; see Figure 2 IS source current ISM peak source current Avalanche ruggedness Tmb = 25 °C tp ≤ 10 µs; pulsed; Tmb = 25 °C EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 31 A; Vsup ≤ 30 V; tp = 0.14 ms; RGS = 50 Ω; unclamped inductive load Min Max – 30 – 30 -20 20 – 48.5 – 76.7 Unit V V V A A – 300 A – 62.5 W -55 150 °C -55 150 °C – 52 A – 208 A – 95 mJ PH6030L_1 Product data sheet Rev. 01 — 29 July 2008 © NXP B.V. 2008. All rights reserved. 2 of 12 NXP Semiconductors 120 Ider (%) 80 03aa23 PH6030L N-channel TrenchMOS logic level FET 120 Pder (%) 80 03aa15 40 40 0 0 50 100 150 200 Tmb (°C) 0 0 50 100 150 200 Tmb (°C) Fig 1. Normalized continuous drain current as a Fig 2. Normalized total power dissipation as a function of mounting base temperature function of mounting base temperature 103 ID […]

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PH6030L Datasheet


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