Part Number: A3S56D40FTP
Function: 256M Double Data Rate Synchronous DRAM
Package: TSOP 66 Pin Type
A3S56D30FTP is a 4-bank x 8,388,608-word x 8bit, A3S56D40FTP is a 4-bank x 4,194,304-word x
16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals
are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and
output data and data strobe are referenced on both edges of CLK. The A3S56D30/40FTP achieves
very high speed clock rate up to 250 MHz.
1. Double data rate architecture ; two data transfers per clock cycle.
2. Bidirectional , data strobe (DQS) is transmitted/received with data
3. Differential clock input (CLK and /CLK)
4. DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
5. Commands entered on each positive CLK edge ;
6. Data and data mask referenced to both edges of DQS
7. 4 bank operation controlled by BA0 , BA1 (Bank Address)
Other data sheets are available within the file: A3S56D30FTP