Part Number : AD5382
Function : 32-Channel, 3 V/5 V, Single-Supply, 14-Bit denseDAC
Manufacturers : Analog Devices
The AD5382 is a complete, single-supply, 32-channel, 14-bit denseDAC® available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. The AD5382 includes an internal software-selectable 1.25 V/2.5 V,10 ppm/°C reference, an on-chip channel monitor function tha multiplexes the analog outputs to a common MON_OUT pin or external monitoring, and an output amplifier boost mode hat allows optimization of the amplifier slew rate. The AD5382 contains a double-buffered parallel interface, which features a 20 ns WR pulse width, an SPI-, QSPI-, MICROWIRE-, DSP-compatible serial interface with interface speeds in excess of 30 MHz and an I2C®-compatible interface that supports a 400 kHz data transfer rate.
An input register followed by a DAC register provides double buffering, allowing the DAC outputs to be updated independently or simultaneously using the LDAC input. Each channel has a programmable gain and offset adjust register that allows the user to fully calibrate any DAC channel. Power consumption is typically 0.25 mA per channel when operating with boost mode disabled.
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Package type: 100-lead LQFP (14 mm × 14 mm)
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,featuring data readback)
Robust 6.5 kV HBM and 2 kV FICDM ESD rating
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Variable optical attenuators (VOAs)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; External REFIN = 2.5 V; all specifications TMIN to TMAX,
unless otherwise noted.
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