D720200AF1 Datasheet – USB3.0 Host Controller

Part Number : D720200AF1, uPD720200AF1

Function : USB 3.0 Host Controller

Package :  176-pin plastic FBGA (10 x 10 mm, 0.65 mm ball pitch)

Manufactures : NEC, Renesas

Images :

D720200AF1 datasheet controller

Description

The D720200AF1 uses a PCI Express Gen 2 system interface bus allowing system designers to easily add up to two USB3.0 SuperSpeed interfaces to systems containing the PCI Express bus interface. When connected to USB 3.0-compliant peripherals, the μPD720200A can transfer information at clock speeds of up to 5 Gbps. The μPD720200A and USB 3.0 standard are fully compliant and backward compatible with the previous USB2.0 Standard. The new USB 3.0 standard supports data transfer speeds of up to ten times faster than those of the previous-generation USB2.0 standard, enabling quick and efficient transfers of large amount of information.

Block Diagram

D720200AF1 pinout

PCI Express Gen2 Interface
: complies with PCI Express Gen2 interface, with 1 lane. This block includes link and PHY layer.

xHCI Controller : handles all supped required for USB 3.0, super-/high-/full-/low-speed. This block
includes register interface from system.

Super-speed Controller I/F : handles super-speed operation in xHCI control block.

High-speed Controller I/F : handles high-speed operation in xHCI control block.

Full/Low-speed Controller I/F : handles full-/low-speed operation in xHCI control block.

USB3.0 SS Link : is link layer defined in USB 3.0 specification, which maintains Link connectivity with USB devices.

USB3.0 SS Root hub : is a hub function in host controller for USB 3.0 port managing.

USB3.0 PHY : for super-speed Tx/Rx

USB2.0 SIE : is Serial Interface Engine, which controls USB 2.0 protocol sequence.

USB2.0 Root hub : is a hub function in host controller for USB 2.0 port managing.

USB2.0 PHY : for high-/full-/low-speed Tx/Rx

Power SW I/F : is connected to external power switch for port power control and over current detection.

SPI Interface : is connected to external serial ROM.

PLL : Internal PLL.

OSC : Internal oscillator block.

Features

1. Universal Serial Bus 3.0 specification Revision 1.0
2. PCI Express Base Specification Revision 2.0
3. Intel’s eXtensible Host Controller Interface (xHCI) Specification Revision 0.96
4. PCI Express Card Electromechanical Specification Revision 2.0
5. PCI Bus Power Management Interface Specification Revision 1.2
6. Support USB legacy function
7. Supports Serial Peripheral Interface (SPI) type ROM
8. Supports PCI Bus Power Management Interface Specification revision 1.2
9. Operational registers are direct-mapped to PCI memory space
10. Supports Serial Peripheral Interface (SPI) type ROM
11. System clock: 24 MHz crystal or 48MHz external clock.
12. 3.3 V and 1.05 V power supply

 

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