contains four master slave flip-flops and additional gating to provide a divide-by two counter and a three-stage binary counter for which the count cycle length is divide-by-five. The counter has a gated zero reset and also has gated set to-nine inputs for use in BCD nine’s complement applications.

To use the maximum count length (decade or four-bit binary), the B input is connected to the QAoutput. The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the counters by connecting the QDoutput to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.

Logic Diagram

Features:

1. Typical power dissipation : 90A, 145 mW

2. Count frequency : 42 MHz

Other data sheets are available within the file: 74HC90, DM7490A, DM7490AN