MT41J64M16LA-187 Datasheet – 8 Meg x 16, DDR3 SDRAM

Part Number : MT41J64M16LA-187

Function : 8 Meg x 16 x 8 Banks, DDR3 SDRAM

Package : 96-FBGA Package

Manufacturers : Micron Technology


MT41J64M16LA-187 datasheet sdram


The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clockcycle data transfers at the I/O pins.


1. VDD = VDDQ = +1.5V ±0.075V
2. 1.5V center-terminated push/pull I/O
3. Differential bidirectional data strobe
4. 8n-bit prefetch architecture
5. Differential clock inputs (CK, CK#)
6. 8 internal banks
7. Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals


1. Configuration
(1) 256 Meg x 4 256M4
(2) 128 Meg x 8 128M8
(3) 64 Meg x 16 64M16

4. FBGA package (Pb-free) – x4, x8
(1) 78-ball FBGA (8mm x 11.5mm) Rev. F JP
(2) 78-ball FBGA (9mm x 11.5mm) Rev. D HX
(3) 86-ball FBGA (9mm x 15.5mm) Rev. B BY

Other data sheets within the file : MT41J64M16LA-187E, MT41J64M16LA-187E:B

MT41J64M16LA-187 Datasheet PDF