Part Number: MX25L25635E
Function: 256M-Bit FLASH MEMORY
Package: SOP 16 Pin Type
MX25L25635E is 268,435,456 bits serial Flash memory, which is configured as 33,554,432 x 8 internally. When it is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. The features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte), block (32K-byte/64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.
HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1532 REV. 0.01, NOV. 18, 2009 1 MX25L25635E Contents Features… 5 GENERAL Description.. 7 Table 1. Additional Features … 7 PIN CONFIGURATION. 8 PIN Description… 8 BLOCK DIAGRAM. … 9 DATA PROTECTION. .. 10 Table 2. Protected Area Sizes… 11 Table 3. 4K-bit Secured OTP Definition 11 Memory Organization. … 12 Table 4. Memory Organization. 12 DEVICE OPERATION. 13 Figure 1. Serial Modes Supported (for Normal Serial mode) 13 HOLD Features.. 14 Figure 2. Hold Condition Operation . 14 COMMAND Description. … 15 Table 5. Command Sets 15 (1) Write Enable (WREN).. […]
MX25L25635E is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.