Part Number : SSTV16859
Function : 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
Package : TSSOP 64-Pin, LFBGA 96-Ball Pin
Manufacturers : Philips Electronics
The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. All inputs are compatible with the JEDEC standard for SSTL_2 with VREFnormally at 0.5*VDD, except the LVCMOS reset(RESET) input. All outputs are SSTL_2, Class II compatible which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTV16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz.
1. Stub-series terminated logic for 2.5 V VDD(SSTL_2)
2. Optimized for stacked DDR (Double Data Rate) SDRAM applications
3. Supports SSTL_2 signal inputs as per JESD 8–9
4. Flow-through architecture optimizes PCB layout
5. ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114.
6. Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA.
7. Supports efficient low power standby operation
8. Full DDR 200/266 solution for stacked DIMMs at 2.5 V when used with PCKV857
9. See SSTV16857 for JEDEC compliant register support in unstacked DIMM applications
10. See SSTV16856 for driver/buffer version with mode select.
Other data sheets within the file : SSTV16859BS, SSTV16859DGG, SSTV16859EC