The MC68HC812A4 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include a 16-bit central processing unit(CPU12), a Lite integration module (LIM), two asynchronous serial communications interfaces (SCI0 and SCI1), a serial peripheral interface (SPI), a timer and pulse accumulation module, an 8-bit analog to-digital converter (ATD), 1-Kbyte RAM, 4-Kbyte EEPROM, and memory expansion logic with chip selects, key wakeup ports, and a phase-locked loop (PLL).
1. Low-Power, High-Speed M68HC12 CPU
2. Power Saving STOP and WAIT Modes
3. Single-Wire Background Debug Mode
4. Non-Multiplexed Address and Data Buses
5. Seven Programmable Chip Selects with Clock Stretching (Expanded Modes)
6. 16-Bit Pulse Accumulator
7. Real-Time Interrupt Circuit
8. Computer Operating Properly (COP) Watchdog
9. Clock Monitor
10. Phase-Locked Loop
Other data sheets are available within the file: MC68HC812A4PV8, MC68HC812A4MPV8, MC68B812A4PV8
The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs.
One latch enable (LE) input and one output enable (OE) are provided per 8-bit section. The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition the latches are transparent, therefore a latch output will changeeach time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the nDn inputs at a set-up time preceding the LOW-to-HIGH transition of LE. When OEis LOW, the contents of the eight latches are available at the outputs. When OEis HIGH, the outputs go to the high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches.
1. Wide supply voltage range from 1.2 V to 3.6 V
2. Complies with JEDEC standard JESD8-B
3. CMOS low power consumption
4. MULTIBYTE flow-through standard pin-out architecture
5. Low inductance multiple VCCand GND pins for minimum noise and ground bounce
6. Direct interface with TTL levels
7. All data inputs have bus hold
8. Output drive capability 50 Ohm transmission lines at 85 ‘C
9. Current drive +-24 mA at VCC= 3.0 V
Other data sheets are available within the file: 74ALVCH16373DGG, 74ALVCH16373DL