SH88F4051 Datasheet – Microcontroller with 10-bit ADC – SINO

Part Number : SH88F4051, SH88F2051

Function : Microcontroller with 10-bit ADCs

Package : SOP, DIP, TSSOP 20 Pin

Manufacturers : SINO WEALTH

Image :

sh88f4051-microcontroller

Description

SH88F2051 / SH88F4051 is a high-speed high-efficiency 8051 compatible single-chip. At the same oscillation frequency, compared with the traditional 8051 chip it has run faster and superior characteristics.

The SH88F2051 / SH88F4051 retains most of the features of the standard 2051 chip. These features include built-in 256-byte RAM and two 16-bit timer / counters, one UART and external interrupts INT0, INT1, INT2. In addition, SH88F2051 / SH88F4051 also integrates 256 bytes of external RAM, compatible with 8052 chip 16-bit timer / counter(Timer2). The microcontroller also includes a 4K / 8K byte Flash block for program and data.

SH88F2051 / SH88F4051 not only integrates the EUART standard communication module, but also integrates with built-in comparison function ADC, PWM timer and other modules.

 

Pinout

sh88f4051-datasheet-pinout

 

Features

1. Based on the 8051 compatible instruction 8-bit microcontroller
2. Flash ROM: 4K / 8K bytes
3. RAM: internal 256 bytes, external 256 bytes
4. 512 bytes of on-chip EEPROM memory space

Block Diagram

sh88f4051-block-diagram

 

 

SH88F4051 Datasheet

 

Related articles across the web

TVP7002 PDF – Triple 8/10-bit, 165/110MSPS Video ADC

Part Number : TVP7002

Function : TRIPLE 8-/10-BIT 165-/110-MSPS VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL

Package : 100-PIN PLASTIC FLATPACK PowerPAD

Manufacturers : Texas Instruments

Image :

TVP7002 datasheet

 

Description :

The TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The  device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA  standard of UXGA (1600 × 1200) resolution at a 60-Hz screen refresh rate, and in video environments for the  digitizing of digital TV formats, including HDTV up to 1080p.

The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer. The TVP7002 also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz. All programming of the device is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.

 

Datasheet PDF Download


TVP7002 pdf

Other data sheets within the file :  TVP7002PZP, TVP7002PZPR