MAX121CAP Datasheet PDF – 308ksps ADC with DSP

Part Number : MAX121CAP

Function : 308ksps ADC with DSP interface and 78dB SINAD

Package : SSOP  20 Pin Type

Manufacturers : Maxim Integrated


MAX121CAP Datasheet

Description :

The MAX121 is complete, BiCMOS, serial-output, sampling 14-bit analog-to-digital converter (ADC) that combines an on-chip track/hold and a low-drift, low-noise, buried-zener voltage reference with fast conversion speed and low power consumption. The throughtput rate is as high as 308K samples per second(ksps). The full-scale analog input range is +-5V.

Pinouts :

MAX121CAP pinout


1. 14-Bit Resolution
2. 2.9μs Conversion Time/308ksps Throughput
3. 400ns Acquisition Time
4. Low Noise and Distortion
5. 210mW Power Dissipation
6. Continuous-Conversion Mode Available


1. Digital Signal Processing
2. Audio and Telecom Processing
3. Speech Recognition and Synthesis
4. DSP Servo Control
5. Spectrum Analysis

Other data sheets within the file : MAX121, MAX121C, MAX121C/D, MAX121CPE

MAX121CAP Datasheet PDF Download

MAX121CAP pdf


TVP7002 Datasheet PDF – Triple 8/10-bit, 165/110MSPS Video ADC

Part Number : TVP7002



Manufacturers : Texas Instruments

Image :

TVP7002 datasheet


Description :

The TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The  device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA  standard of UXGA (1600 × 1200) resolution at a 60-Hz screen refresh rate, and in video environments for the  digitizing of digital TV formats, including HDTV up to 1080p.

The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer. The TVP7002 also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz. All programming of the device is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.


Datasheet PDF Download

TVP7002 pdf

Other data sheets within the file :  TVP7002PZP, TVP7002PZPR