The DM7490A monolithic counter contains four master slave flip-flops and additional gating to provide a divide-by two counter and a three-stage binary counter for which the count cycle length is divide-by-five. The counter has a gated zero reset and also has gated set to-nine inputs for use in BCD nine’s complement applications.
To use the maximum count length (decade or four-bit binary), the B input is connected to the QAoutput. The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the counters by connecting the QDoutput to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.
Other data sheets within the file : 7490, DM7490A, DM7490AN
This circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change together when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally as sociated with asynchronous (ripple-clock) counters.
The outputs of the four master-slave flip-flops are triggered by a low-to-high level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is held high.