Function : 3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer
Package : 52-Lead Type
Manufacturers : Motorola, Renesas
The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device meets the needs of the most demanding clock applications.
The MPC9449 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 200 MHz. The device has 15 identical outputs, organized in four output banks. Each output bank provides a retimed or frequency divided copy of the input signal with a near zero skew. The output buffer supports driving of 50Ω terminated transmission lines on the incident edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines.
• 15 LVCMOS compatible clock outputs
• Two selectable LVCMOS and one differential LVPECL compatible clock inputs
• Selectable output frequency divider (divide-by-one and divide-by-two)
• Maximum clock frequency of 200 MHz
• Maximum clock skew of 200 ps
• High-impedance output control
The 74HC541 is an advanced high-speed CMOS OCTAL BUS BUFFER (3-STATE) fabricated with silicon gate C2MOS technology. The M74HC541 is a non inverting buffer. The 3-STATE control gate operates as a two input AND such that if either G1and G2are high, all eight output are in the high impedance state.
1. High Speed : tPD = 9ns (TYP.) at VCC = 6V
2. LOW POWER DISSIPATION : ICC = 4µA(MAX.) at TA=25°C
3. HIGH NOISE IMMUNITY : VNIH = VNIL = 28 % VCC (MIN.)
4. SYMMETRICAL OUTPUT IMPEDANCE : |IOH| = IOL = 6mA (MIN)
5. BALANCED PROPAGATION DELAYS : tPLH ≅ tPHL
6. WIDE OPERATING VOLTAGE RANGE : VCC (OPR) = 2V to 6V
7. PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 541