The 74AC245 octal bus transceivers are designed for asynchronous two-way communication
between data buses. The control-function implementation minimizes external timing
requirements. When the output-enable (OE) is low, the device passes noninverted data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction control (DIR) input.
A high on (OE) disables the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OEshould be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
1. 2-V to 6-V VccOperation
2. Inputs Accept Voltages to 6 V
3. Max tpd of 7 ns at 5 V
74AC245 Datasheet PDF Download
Other data sheets within the file : SN74AC245, 54AC245, SN54AC245,
These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192 x 8 bits (M24C64) and 4096 x 8 bits (M24C32). I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master.
Other data sheets within the file : M24C64, M24C64-W, M24C64-R