AD800 Datasheet – Clock Recovery and Data Retiming

This post explains for the semiconductor AD800.

The Part Number is AD800. The Package is 20PIn SMD or Cerdip Dip Pin Type.

The function of this semiconductor is Clock Recovery and Data Retiming Phase-Locked Loop.

Manufacturers : Analog Devices

Image and pinout :

AD800 datasheet


Description :

The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data retiming on Non-Return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps. The products described here have been defined to work with standard telecommunications bit rates. 45 Mbps DS-3 and 52 Mbps STS-1 are supported by the AD800-45 and AD800-52 respectively.

Unlike other PLL-based clock recovery circuits, these devices do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data.


AD800 pinout



1. Standard Products
(1) 44.736 Mbps – DS-3
(2) 51.84 Mbps – STS-1
(3) 155.52 Mbps – STS-3 or STM-1

2. Accepts NRZ Data, No Preamble Required
3. Recovered Clock and Retimed Data Outputs
4. Phase-Locked Loop Type Clock Recovery—No Crystal Required
5. Random Jitter: 20° Peak-to-Peak
6. Pattern Jitter: Virtually Eliminated
7. 10KH ECL Compatible
8. Single Supply Operation: –5.2 V or +5 V
9. Wide Operating Temperature
10. Range: –40°C to +85°C

Ordering Number : AD802-155BR , AD802-155KR


AD800 Datasheet

AD800 pdf

MPC9449 Datasheet – Clock Fanout Buffer

Part Number : MPC9449

Function : 3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer

Package : 52-Lead Type

Manufacturers : Motorola, Renesas

Image :

MPC9449 datasheet


Description :

The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device meets the needs of the most demanding clock applications.

Block Diagram

The MPC9449 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 200 MHz. The device has 15 identical outputs, organized in four output banks. Each output bank provides a retimed or frequency divided copy of the input signal with a near zero skew. The output buffer supports driving of 50Ω terminated transmission lines on the incident edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines.



• 15 LVCMOS compatible clock outputs
• Two selectable LVCMOS and one differential LVPECL compatible clock inputs
• Selectable output frequency divider (divide-by-one and divide-by-two)
• Maximum clock frequency of 200 MHz
• Maximum clock skew of 200 ps
• High-impedance output control

Other data sheets within the file : MPC-9449

MPC9449 Datasheet PDF Download

MPC9449 pdf