ALC887 Datasheet – 7.1 Channel High Definition Audio Codec

This post explains for the semiconductor ALC887, ALC887-GR.

The Package is LQFP-48 Type.

The function of this semiconductor is 7.1 Channel High Definition Audio Codec.

Manufacturers : Realtek Microelectronics

Preview images :

1 page
ALC887 image

Description :

The ALC887 is a 7.1 Channel High Definition Audio Codec with two independent SPDIF outputs.
Featuring eight channels of DAC support 7.1 sound playback, and integrates two stereo ADC that can
support a stereo microphone, and feature Acoustic Echo Cancellation (AEC), Beam Forming (BF), and
Noise Suppression (NS) for voice applications.

ALC887 is designed not only to meet the premium audio performance requirements in current WLP3.10
(Windows Logo Program), but provides better characteristics for future WLP. That brings user real high
fidelity of sound quality. […]



1. Meets premium audio requirements for Microsoft WLP 3.10
2. Meets stricter performance requirements for future WLP
3. High-performance DACs with 97dB Signal-to-Noise Ratio (SNR), ADCs with 90dB SNR
4. Four stereo DACs (8 channels) support 16/20/24-bit PCM format for 7.1 sound playback.
5. Two stereo ADCs (4 channels) support 16/20/24-bit PCM format recording simultaneously
6. All DACs supports 16/20/24-bit, 44.1k/48k/96k/192kHz sample rate
7. All ADCs supports 16/20/24-btt, 44.1k/48k/96k/192kHz sample rate
8. Two independent SPDIF-OUT converters support 16/20/24-bit, 44.1k/48k/88.2k/96k/192kHz sample
rate. One converter for normal SPDIF output, the other outputs an independent digital stream to the
HDMI transmitter


ALC887 Datasheet

Hi3531 Datasheet – H.264 Codec Processor

Part Number : Hi3531

Function : H.264 Codec Processor

Package : 25mm x 25mm and a pitch of 0.65mm Type ( 817 pins )

Manufacturers : Hisilicon Technologies

Image :

Hi3531 Codec Processor

Description :

The Hi3531 is a professional high-performance SoC designed for multi-channel D1 and HD DVR and NVR. With the embedded high-performance dual-core A9 processor, H264 codec engine (supporting a maximum of 5-channel 1080p real-time codec complying with multiple protocols), and dedicated TOE network acceleration module, the Hi3531 meets the rising demand for HD and network applications. The Hi3531 also provides outstanding video pre-processing and post-processing features, various codec algorithms, and multi-channel HD output capability. These features guarantee users a high-quality image experience. In addition, the Hi3531 supports multiple integrated peripheral interfaces to meet customer requirements for functionality, features, and image quality, while reducing the cost. By
using the dedicated video cascade technology, Hi3531s and Hi3532s can be cascaded to provide superior encoding and decoding capabilities.

Key Specifications

1. Processor
(1) ARM Cortex A9 dual cores
− Up to 930 MHz
− 32 KB I-cache and 32 KB D-cache
− 256 KB L2 cache

2. Video and Graphic Processing
(1) 3D de-interlacing, image enhancement, edge enhancement, and 3D denoise
(2) Anti-flicker
(3) 1/16x to 8x video scaling
(4) 1/2x to 2x graphic scaling
(5) OSD overlay of eight regions
(6) Alpha blending of the video layer and graphics layers

Block Diagram
Hi3531 datasheet pdf

Typical Applications

1. DVRs with a Single Hi3531
(1) 16D1+16CIF Encoding+4D1 Decoding DVR
– 16D1+16CIF dual streams real-time encoding +16 fps D1 JPEG snapshot+4D1 real-time decoding
(2) 8D1 Simultaneous Encoding and Decoding DVR
– 16D1+16CIF dual streams real-time encoding +16 fps D1 JPEG snapshot+4D1 real-time decoding
4-Channel HD Simultaneous Encoding and Decoding DVR
(3) 4x720p+4xQVGA dual streams real-time encoding +4 fps 720p JPEG snapshot+4x720p real-time decoding


Hi3531 Datasheet PDF Download