The HC696/697 are high speed CMOS up/down counters fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The HC696/698 are BCD DECADE COUNTER, and the HC697/699 are 4-BIT BINARY COUNTER. Both devices have register. They count on the positive edge of the counter clock input (CCK) when selected by the ”Counter Mode”. If the input U/D is held ”H”, the internal counter counts up, and held ”L”, counts down.
1. High Speed : f MAX = 50 MHz (Typ.) at Vcc = 5 V 2. Low Power Dissipation : Icc = 4 uA (Max.) at Ta = 25’C 3. High Noise Immunity : Vnih = Vnil = 28% Vcc (Min.) 4. Wide Operating Voltage Range : Vcc(OPR) = 2V to 6 V
Other data sheets within the file : M74HC696M, 54HC697, 54HC698, 54HC699, 74HC696
This is one of the semiconductor types. Package is PDIP 14 Pin Package.
This part name is SN74LS90N. This product has Decade Counter function.
The manufacturers of this product is Texas Instruments.
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Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the ’90A and ‘LS90, divide-by-six for the ’92A and ‘LS92, and the divide-by eight for the ’93A and ‘LS93. All of these counters have a gated zero reset and the ’90A and ‘LS90 also have gated set-to-nine inputs for use in BCD nine’s complement applications.
To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the QA output. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the ’90A or ‘LS90 counters by connecting the QD output to the CKA input and applying the input count to the CKB input which gives a divide-by-ten square wave at output QA.