The ’HCT138 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
Other data sheets within the file : 54HCT138FK, 54HCT138J, 54HCT138W, 74HCT138D
Function : 4-Line to 16-Line Decoders / Demultiplexers
Package : DIP 14 Pin Type
Manufacturers : National, Fairchild, TI
Each or these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are low. The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the other strobe input low. When either strobe input is high, all outputs are high. These demultiplexers are ideally suited for implementing high-performance memory decoders. All inputs are buffered and input clamping diodes are provided to minimize transmission-line effects and thereby simplify system design.
1. Decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs 2. Performs the demultiplexing function by distributing data from one input line to any one of 16 outputs 3. Input clamping diodes simplify system design 4. High fan-out, low-impedance, totem-pole outputs 5.Typical power dissipation 170 mW
Other data sheets within the file : 54154, DM74154, SN74154, 74LS154, 74HC154