Function : DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
Package: DIP, SOP 14 Pin Type
Image and Pinout
The SN54LS74 / 74LS74N dual edge-triggered flip-flop utilizes Schottky TTL circuitryto produce high speed D-type flip-flops. Each flip-flop hasindividual clear and set inputs, and also complementary Q and Qoutputs. Informationat input D is transferred to the Q output on thepositive-going edge of the clock pulse. Clock triggering occursat a voltage level of the clock pulseand is not directly related to the transition time of the positive-going pulse.When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.
These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The 74147 and 74LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.
The 74148 and 74LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54/74LS load, respectively.
1. Encode 10-Line Decimal to 4-Line BCD
2. Applications Include: