The Realtek RTL8211E-VB-CG/RTL8211E-VL-CG/RTL8211EG-VB-CG are highly integrated Ethernet transceivers that comply with 10Base-T, 100Base-TX, and 1000Base-T IEEE 802.3 standards. They provide all the necessary physical layer functions to transmit and receive Ethernet packets over CAT.5 UTP cable.
The RTL8211E-VB(VL)/RTL8211EG-VB uses state-of-the-art DSP technology and an Analog Front End (AFE) to enable high-speed data transmission and reception over UTP cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented in the RTL8211E-VB(VL)/RTL8211EG-VB to provide robust transmission and reception capabilities at 10Mbps, 100Mbps, or 1000Mbps.
Data transfer between MAC and PHY is via the Reduced Gigabit Media Independent Interface (RGMII) or Gigabit Media Independent Interface (GMII) for 1000Base-T, 10Base-T, and 100Base-TX. The RTL8211E-VB and RTL8211EG-VB support 3.3V or 2.5V signaling for RGMII/GMII. The RTL8211E-VL supports 1.5/1.8V signaling for RGMII.
The Am79C972 PCnet-FAST+ controller is a highly integrated 32-bit full-duplex, 10/100-Megabit per second (Mbps) Ethernet controller solution, designed to address high-performance system application requirements. It is a flexible bus mastering device that can be used in any application, including network-ready PCs and bridge/router designs. The bus master architecture provides high data throughput and low CPU and system bus utilization. The Am79C972 controller is fabricated with advanced low-power 3.3-V CMOS process to provide low operating current for power sensitive applications.
The Am79C972BKC PCnet-FAST+ controller also has several enhancements over its predecessor, the Am79C971 PCnet-FASTdevice. In addition to integrating the SRAM on chip, it further reduces system implementation cost by the addition of a new EEPROM programmable pin (PHY_RST), an internal oscillator circuit eliminating the need for an external crystal, and the integration of the PAL function needed for Magic Packet application. The PHY_RST pin is implemented to reset the external PHY without increasing the load to the PCI bus and to block RSTto the PHY when PG input is LOW.
Related AMD Products
Am79C90 : CMOS Local Area Network Controller for Ethernet (C-LANCE) Am7996 : IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Am79C98 : Twisted Pair Ethernet Transceiver (TPEX) Am79C100 : Twisted Pair Ethernet Transceiver Plus (TPEX+) Am79865 : 100 Mbps Physical Data Transmitter (PDT) Am79866A : 100 Mbps Physical Data Receiver (PDR) Am79C871 : Quad 100BASE-X Transceiver for Repeater Am79C940 : Media Access Controller for Ethernet (MACE™) Am79C961A : PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller Am79C965 : PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses) Am79C970A : PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Am79C971 : PCnet-FAST Single-Chip Full-Duplex 10/100 Ethernet Controller for PCI Local Bus
Other data sheets within the file : AM79C972BKIW, AM79C972BVC, AM79C972BVCW, AM79C972BVIW