Offered in 128Mx8bit, the K9F1G08U0E is a 1G-bit NAND Flash Memory with spare 32M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 400s on the (2K+64)Byte page and an erase operation can be performed in typical 4.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte.
The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1G08U0E extended reliability by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08U0E is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
1. Voltage Supply
– 3.3V Device(K9F1G08U0E) : 2.7V ~ 3.6V
– Memory Cell Array : (128M + 4M) x 8bit
– Data Register : (2K + 64) x 8bit
3. Automatic Program and Erase
– Page Program : (2K + 64)Byte
– Block Erase : (128K + 4K)Byte
Function: 1 Mbit Low Voltage Paged Flash Memory With 20 MHz Serial SPI Bus Interface
Package: SOP 8 Pin
1. 1 Mbit PAGED Flash Memory
2. 128 BYTE PAGE PROGRAM IN 3 ms TYPICAL
3. 256 Kbit SECTOR ERASE IN 1 s TYPICAL
4. BULK ERASE IN 2 s TYPICAL
5. SINGLE 2.7 V to 3.6 V SUPPLY VOLTAGE
6. SPI BUS COMPATIBLE SERIAL INTERFACE
7. 20 MHz CLOCK RATE AVAILABLE
8. SUPPORTS POSITIVE CLOCK SPI MODES
9. DEEP POWER DOWN MODE (1 µA TYPICAL)
10. ELECTRONIC SIGNATURE
11. 10,000 ERASE/PROG CYCLES PER SECTOR
12. 20 YEARS DATA RETENTION
13. –40 TO 85°C TEMPERATURE RANGE
The 25P10VP ( M25P10 ) is an 1 Mbit Paged Flash Memory fabricated with STMicroelectronics High Endurance CMOS technology. The memory is accessed by a simple SPI bus compatible serial interface. The bus signals are a serial clock input (C), a serial data input (D) and a serial data output (Q).
The device connected to the bus is selected when the chip select input (S) goes low. Data is clocked in during the low to high transition of clock C, data is clocked out during the high to low transition of clock C
Serial Output (Q)
The output pin is used to transfer data serially out of the memory. Data is shifted out on the falling edge of the serial clock.
Serial Input (D)
The input pin is used to transfer data serially into the device. It receives instructions, addresses,
and the data to be programmed. Input is latched on the rising edge of the serial clock.
Serial Clock (C)
The serial clock provides the timing of the serial interface. Instructions, addresses, or data present
at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes
after the falling edge of the clock input.
Other data sheets are available within the file: M25P10-VMW6T, M25P10-AVMN6TP/X