The 74HC74AP is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CLOCK pulse.
1. High speed: fmax = 77 MHz (typ.) at VCC = 5 V 2. Low power dissipation: ICC = 2 μA (max) at Ta = 25°C 3. High noise immunity: VNIH = VNIL = 28% VCC (min) 4. Output drive capability: 10 LSTTL loads 5. Symmetrical output impedance: |IOH| = IOL = 4 mA (min) 6. Balanced propagation delays: tpLH −∼ tpHL 7. Wide operating voltage range: VCC (opr) = 2 to 6 V 8. Pin and function compatible with 74LS74
Other data sheets within the file : TC74HC74AF, 74HC74AF ( SOP 14 Pin )
These devices are positive edge triggered flip-flops. The difference between HD74HC564 and HD74HC574 is only that the former has inverting outputs and the latter has noninvertering outputs.
Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or outputs on positive going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
1. High Speed Operation: tpd (Clock to Output) = 13 ns typ (CL = 50 pF) 2. High Output Current: Fanout of 15 LSTTL Loads 3. Wide Operating Voltage: VCC = 2 to 6 V 4. Low Input Current: 1 μA max 5. Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C)
Other data sheets within the file : HD74HC564FPEL, HD74HC564RPEL, HD74HC574FPEL, HD74HC574P