74F109 Datasheet PDF – Dual JK, Flip-Flop

Part Number : 74F109

Function : Dual JK Positive Edge-Triggered Flip-Flop

Package : DIP, SOP, SOIC 16 Pin type

Manufacturers : Fairchild Semiconductor

Pinouts :

74F109 datasheet


Description :

The 74F109 consists of two high-speed, completely independent transition clocked JKflip-flops. The clocking operationis independent of rise and fall times of the clock waveform.
The JKdesign allows operation as a D-type flip-flop (referto F74 data sheet) by connecting the J and Kinputs.

Asynchronous Inputs :

1. LOW input to SD sets Q to HIGH level

2. LOW input to CD sets Q to LOW level

3. Clear and Set are independent of clock

4. Simultaneous LOW on CD and SD makes both Q and Q HIGH

Absolute Maximum Ratings :

1. Storage Temperature : – 65°C to +150°C

2. Ambient Temperature under Bias : – 55°C to +125°C

3. Junction Temperature under Bias : – 55°C to +175°C

4. VCC Pin Potential to Ground Pin : – 0.5V to +7.0V

5. Input Voltage (Note 2) : – 0.5V to +7.0V

6. Input Current (Note 2) : -30 mA to +5.0 mA


Other data sheets within the file :

74F109PC, 74F109SC, 74F109SCX, 74F109SJ

74F109 Datasheet PDF Download

74F109 pdf

Related articles across the web

VC16374ADGG – 16-bit edge triggered D-type flip-flop

Part Number : VC16374ADGG

Function : 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Package : TSSOP, SSOP 48 Pin type

Manufacturers : NXP Semiconductors. , Philps Semicondcutor

Pinouts :

VC16374ADGG datasheet


Description :

The 74LVC(H)16374A, VC16374ADGG is a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. The 74LVC16374A consists of 2 sections of eight positive edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment


Features :

1. 5 V tolerant inputs/outputs for interfacing with 5 V logic

2. Wide supply voltage range from 1.2 V to 3.6 V

3. CMOS low power consumption

4. Multibyte flow-through standard pinout architecture

5. Low inductance multiple supply pins for minimum noise and ground bounce

6. Direct interface with TTL levels

7. All data inputs have bus hold (74LVCH16374A only)

8. High-impedance outputs when VCC = 0 V


VC16374ADGG Datasheet PDF Download

VC16374ADGG pdf

Other data sheets within the file :

74LVC16374ABX, 74LVC16374ADGG, 74LVC16374ADL,

74LVCH16374ABX, 74LVCH16374ADGG