The SN54LS74A / 74LS74A dual edge-triggered flip-flop utilizesSchottky TTL circuitryto produce high speed D-type flip-flops. Each flip-flop hasindividual clear and set inputs, and also complementary Q and Qoutputs. Informationat input D is transferred to the Q output on thepositive-going edgeof the clock pulse. Clock triggering occursat a voltage level of the clock pulseand is not directly related to the transition time of the positive-going pulse.When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.
Other data sheets within the file : 54LS74, SN54LS74J, SN74LS74D, SN74LS74N, 74LS74
The MC74HC76 is identical in pinout to the LS76. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip–flop is negative-edge clocked and has active–low asynchronous Set and Reset inputs. The HC76 is identical in function to the HC112, but has a different pinout.
1. Output Drive Capability: 10 LSTTL Loads 2. Outputs Directly Interface to CMOS, NMOS and TTL 3. Operating Voltage Range: 2 to 6V 4. Low Input Current: 1mA 5. High Noise Immunity Characteristic of CMOS Devices 6. In Compliance With the JEDEC Standard No. 7A Requirements 7. Chip Complexity: 100 FETs or 25 Equivalent Gates
Other data sheets within the file : 74HC76, MC74HC76, MC74HC76N, 7476, MC74HC76D