The Intel 8088 is a high performance microprocessor implemented in N-channel, depletion load, silicon gate technology (HMOS-II), and packaged in a 40-pin CERDIP package. The processor has attributes of both 8-and 16-bit microprocessors. It is directly compatible with 8086 software and 8080/8085 hardware and peripherals. Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin. The 8088 RESET is required to be HIGH for greater than four clock cycles.
Pinout and Block Diagram
1. 8-Bit Data Bus Interface
2. 16-Bit Internal Architecture
3. Direct Addressing Capability to 1 Mbyte of Memory
4. Direct Software Compatibility with 8086 CPU
5. 14-Word by 16-Bit Register Set with Symmetrical Operations
6. 24 Operand Addressing Modes
7. Byte, Word, and Block Operations
8. 8-Bit and 16-Bit Signed and Unsigned Arithmetic in Binary or Decimal, Including Multiply and Divide
The 82375EB/SB PCI-EISA Bridge (PCEB) provides the master/slave functions on both the PCI Local Bus and the EISA Bus. Functioning as a bridge between the PCI and EISA buses, the PCEB provides the address and data paths, bus controls, and bus protocol translation for PCI-to-EISA and EISA-to-PCI transfers. Extensive data buffering in both directions increases system performance by maximizing PCI and EISA Bus efficiency and allowing concurrency on the two buses. The PCEB’s buffer management mechanism ensures data coherency.
The PCEB integrates central bus control functions including a programmable bus arbiter for the PCI Bus and EISA data swap buffers for the EISA Bus. Integrated system functions include PCI parity generation, system error reporting, and programmable PCI and EISA memory and I/O address space mapping and decoding. The PCEB also contains a BIOS Timer that can be used to implement timing loops. The PCEB is intended to be used with the EISA System Component (ESC) to provide an EISA I/O subsystem interface.
Other data sheets within the file : 82375EB, 82375