A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.
• Member of the Texas Instruments Widebus™Family
• EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
• DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without Speed Degradation
• Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs.
One latch enable (LE) input and one output enable (OE) are provided per 8-bit section. The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition the latches are transparent, therefore a latch output will changeeach time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the nDn inputs at a set-up time preceding the LOW-to-HIGH transition of LE. When OEis LOW, the contents of the eight latches are available at the outputs. When OEis HIGH, the outputs go to the high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches.
1. Wide supply voltage range from 1.2 V to 3.6 V
2. Complies with JEDEC standard JESD8-B
3. CMOS low power consumption
4. MULTIBYTE flow-through standard pin-out architecture
5. Low inductance multiple VCCand GND pins for minimum noise and ground bounce
6. Direct interface with TTL levels
7. All data inputs have bus hold
8. Output drive capability 50 Ohm transmission lines at 85 ‘C
9. Current drive +-24 mA at VCC= 3.0 V
Other data sheets within the file : 74ALVCH16373DGG, 74ALVCH16373DL