The TSC80C31 / TSC80C51 is high performance SCMOS versions of the 8051 NMOS single chip 8 bit µC. The fully static design of the TSC80C31/TSC80C51 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.
The TSC80C31/TSC80C51 retains all the features of the 8051 : 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ; two 16 bit timers ; a 5-source, 2-level interrupt structure ; a full duplex serial port ; and on-chip oscillator and clock circuits.
1. Power control modes
2. 128 bytes of RAM
3. 4 K bytes of ROM (TSC80C31/80C51)
4. 32 programmable I/O lines
5. Two 16 bit timer/counter
6. 64 K program memory space
7. 64 K data memory space
The 12C508A from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EEPROM/EPROM/ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (1 µs) except for program branches which take two cycles. The PIC12C5XX delivers performance an order of magnitude higher than its competitors in the same price category.
The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly.
The 12C508A products are equipped with special features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features also improve system cost, power and reliability.
Peripheral Features :
1. 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler
2. Power-On Reset (POR)
3. Device Reset Timer (DRT)
4. Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
5. Programmable code-protection
6. 1,000,000 erase/write cycle EEPROM data memory
7. EEPROM data retention > 40 years
8. Power saving SLEEP mode
9. Wake-up from SLEEP on pin change
10. Internal weak pull-ups on I/O pins
Other data sheets within the file : PIC12C508, PIC12C508A, PIC12C509, PIC12C509A