74HC157 Datasheet PDF – Quad, Multiplexer – NXP

Part Number : 74HC157

Function : Quad 2-input Multiplexer

Package : SO16, SSOP 16, TSSOP16, DHVQFN16 Type

Manufacturers : NXP Semiconductors.

Pinouts :

74HC157 datasheet

Description :

The 74HC157, 74HCT157 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.

The devices are quad 2-input multiplexers which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When Eis HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions.

It can also be used as function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common.

Features

1. Low-power dissipation

2. Complies with JEDEC standard no. 7A

3. Input levels : For 74HC157: CMOS level

4. Non-inverting data path

74HC157 Datasheet PDF Download

74HC157 pdf

Other data sheets within the file : 74HC157BQ, 74HC157D, 74HC157DB, 74HC157N

74HC257 Datasheet – Quad 2-input Multiplexer ( PDF )

Part Number : 74HC257

Function : Quad 2-input multiplexer; 3-state

Package : DIP, SO, SSOP, TSSOP 16 Pin Type

Manufacturers : NXP Semiconductors.

Image and Pinouts :

74HC257 datasheet

 

Description :

The 74HC257, 74HCT257 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). The 74HC257 and 74HCT257 have four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S).

The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when S is HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.

The 74HC257 and 74HCT257 are the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high-impedance OFF-state when OEis HIGH.

Features :

1. Non-inverting data path

2. 3-state outputs interface directly with system bus

3. Complies with JEDEC standard no. 7A

 

Other data sheets within the file :

74HC257D, 74HC257DB, 74HC257N, 74HC257PW, 74HCT257, 74T257

 

74HC257 Datasheet PDF Download


74HC257 pdf