74LS140 Datasheet – Dual 4-input NAND 50Ω Line Drive

Part Number: 74LS140

Function: LSTTL Dual 4-input NAND

Package: DIP 14 Pin Type

Manufacturer: TW, BDTIC


74LS140 Datasheet Pinout


The 74LS140 is 4-input NAND gates, 50-Ohm line drivers.

In computer science, NAND is a logic gate that produces a logical “NOT-AND” output from two logical inputs. In addition to being a fundamental building block of digital circuits, NAND gates are also used to construct other logic gates, such as OR and NOT gates.


Logic symbols

Typical parameters: tpd = 12ns Pd = 4.3mW

74LS140 pinout


74LS140 Logic Table

74LS140 Logic Table


Recommended Operating Conditions

Operating Conditions

74LS140 Datasheet



Other data sheets are available within the file:  54LS140

Related articles across the web

K9F2G08U0B Datasheet – 256M x 8 Bit NAND Flash Memory

Part Number: K9F2G08U0B

Function: 256M x 8 Bit NAND Flash Memory

Package: TSOP 48 Pin

Manufacturer: Samsung


K9F2G08U0B datasheet


Offered in 256Mx8bit, the K9F2G08U0B is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most costeffective solution for the solid state application market. A program operation can be performed in typical 200μs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input.

The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F2G08X0B′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.


K9F2G08U0B Pinout



1. Voltage Supply
(1) 2.7V device(K9F2G08B0B): 2.50V ~ 2.90V
(2) 3.3V device(K9F2G08U0B): 2.70V ~ 3.60V

2. Organization
(1) Memory Cell Array : (256M + 8M) x 8bit
(2) Data Register : (2K + 64) x 8bit

3. Automatic Program and Erase
(1) Page Program : (2K + 64)Byte
(2) Block Erase : (128K + 4K)Byte

4. Page Read Operation
(1) Page Size : (2K + 64)Byte
(2) Random Read : 25µs(Max.)
(3) Serial Access : 25ns(Min.)

5. Command/Address/Data Multiplexed I/O Port


K9F2G08U0B Datasheet PDF Download

K9F2G08U0B pdf

Other data sheets are available within the file:  K9F2G08B0B-P, K9F2G08U0B, K9F2G08U0BP