74VHC273 Datasheet – Octal D-Type Flip-Flop

Part Number : 74VHC273

Function : Octal D-Type Flip-Flop

Package : DIP, SOIC, SOP, TSSOP 20 Pin Type

Manufacturers : Fairchild Semiconductor

Pinouts :

74VHC273 datasheet


Description :

The 74VHC273 is an advanced high speed CMOS Octal D-type flip-flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.

The register has a common buffered Clock (CP) which is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The Master Reset (MR) input will clear all flip-flops simultaneously.


1. High Speed: fMAX=165MHz (typ) at VCC=5V

2. Low power dissipation: ICC=4µA (max) at TA=25°C

3. High noise immunity: VNIH=VNIL=28% VCC(min)

4. Power down protection is provided on all inputs

5. Low noise: VOLP=0.9V (max)

6. Pin and function compatible with 74HC273

7. Leadless DQFN Package

Other data sheets within the file :

74VHC273BQ, 74VHC273M, 74VHC273MTC, 74VHC273SJ

74VHC273 Datasheet PDF Download

74VHC273 pdf

74HC373 Datasheet – Octal D-type Transparent Latch

Part Number : 74HC373

Function : Octal D-type transparent latch; 3-state

Package : DIP, SO, TSSOP DHVQFN 20 Type

Manufacturers : NXP Semiconductors.

Pinouts :

74HC373 datasheet


Description :

The 74HC373, 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.

The device is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches.

The 74HC373, 74HCT373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes.

When LE is LOW the latches store the information that was present at the D inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OEis LOW, the contents of the 8 latches are available at the outputs. When OEis HIGH, the outputs go to the high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches.

Features :

1. 3-state non-inverting outputs for bus oriented applications

2. Common 3-state output enable input

Other data sheets within the file :

74HC373BQ, 74HC373D, 74HC373DB, 74HC373N, 74HCT373DB, 74HCT373


74HC373 Datasheet PDF Download

74HC373 pdf