74ABT273 Datasheet – Octal D-Type Flip-Flop ( PDF )

Part Number: 74ABT273

Function: Octal D-Type Flip-Flop

Package: SOP, SOIC, SSOP, TSSOP 20 Pin Type

Manufacturer: Fairchild Semiconductor


74ABT273 datasheet



The 74ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MRinput. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.


1. Eight edge-triggered D-type flip-flops

2. Buffered common clock

3. Buffered, asynchronous Master Reset

4. See ABT377 for clock enable version

5. See ABT373 for transparent latch version

6. See ABT374 for 3-STATE version

7. Output sink capability of 64 mA, source capability of 32 mA

8. Guaranteed latchup protection

9. High impedance glitch free bus loading during entire power up and power down cycle

10. Non-destructive hot insertion capability

11. Disable time less than enable time to avoid bus contention


Other data sheets are available within the file:


74ABT273 Datasheet PDF Download

74ABT273 pdf

HD74HC564P Datasheet PDF – Octal D-type Flip-Flop – Hitachi

Part Number: HD74HC564P

Function: Octal D-type Flip-Flops (with 3-state outputs)

Package: DIP 20 Pin type

Manufacturer: Hitachi ( Renesas Electronics )

Images :
HD74HC564P datasheet


These devices are positive edge triggered flip-flops. The difference between HD74HC564P and HD74HC574 is only that the former has inverting outputs and the latter has noninvertering outputs.

Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive going transitions of the clock (CK) input. when a high logic level is applied to the output cotrol (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.


1. High Speed Operation: tpd (Clock to Output) = 13 ns typ (CL = 50 pF)

2. High Output Current: Fanout of 15 LSTTL Loads

3. Wide Operating Voltage: VCC = 2 to 6 V

4. Low Input Current: 1 μA max

5.  Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C)



Other data sheets are available within the file: 74HC564, HD74HC564, HD74HC574, HD74HC574P

HD74HC564P Datasheet PDF Download

HD74HC564P pdf