These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units.
Information present at a data(D) input is transferred to the Q output when the enable is HIGH, and the Q output will follow the data input as long as the enable remains HIGH. When the enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go HIGH.
Other data sheets within the file : 74LS75, DM74LS75, DM74LS75M
The SN65LVCP114 is an asynchronous, protocol-agnostic, low-latency QUAD mux, linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device linearly compensates for channel loss in backplane and active-cable applications. The architecture of SN65LVCP114 linear-redriver is designed to work effectively with ASIC or FPGA products implementing digital equalization using decision feedback equalizer (DFE) technology.
The SN65LVCP114 mux, linear-redriver preserves the integrity (composition) of the received signal, ensuring optimum DFE and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver solution while at the same time extending the effectiveness of DFE.
1. Quad 2:1 Mux and 1:2 Demux
2. Multi-Rate Operation up to 14.2 Gbps Serial Data Rate
3. Linear Receiver Equalization Which Increases Margin at System Level of Decision Feedback
4. Bandwidth: 18 GHz, Typical
5. Per-Lane P/N Pair Inversion
6. Port or Single Lane Switching
1. High-Speed Redundancy Switch in Telecom and Data Communication
2. Backplane Interconnect for 10G-KR, 16GFC