74ABT16373 Datasheet – 16-bit, Transparent Latch

Part Number : 74ABT16373

Function : 16-bit transparent latch (3-State)

Package : DIP, SOP 48 Pin Type

Manufacturers : Philips Electronics ( https://www.nxp.com/ )

Pinouts :

74ABT16373 datasheet

 

Description :

The 74ABT16373B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT16373 device is a dual octal transparent latch coupled to two sets of eight 3-State output buffers. The two sections of the device are controlled independently by Enable (nE) and Output Enable (nOE) control gates.

The data on each set of D inputs are transferred to the latch outputs when the Latch Enable (nE) input is HIGH. The latch remains transparent to the data inputs while nE is HIGH, and stores the data that is present one set-up time before the HIGH-to-LOW enable transition.

 

Features :

1. 16-bit transparent latch

2. Multiple VCC and GND pins minimize switching noise

3. Power-up 3-State

4. Live insertion/extraction permitted

5. Power-up reset

6. 3-State output buffers

Other data sheets within the file :

74ABT16373B, 74ABT16373BDGG, 74ABT16373BDL, 74ABTH16373BDL, 7416373

 

74ABT16373 Datasheet PDF Download


74ABT16373 pdf

PCA9517A Datasheet PDF – Level Translating I2C-bus Repeater

Part Number : PCA9517A

Function : Level translating I2C-bus repeater

Package : SO, TSSOP 8 Pin Type

Manufacturers : NXP Semiconductors.

Pinouts :

PCA9517A datasheet

 

Description :

The PCA9517A is a CMOS integrated circuit that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2 C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using the PCA9517A enables the system designer to isolate two halves of a bus for both voltage and capacitance.

The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PCA9517A is unpowered. The 2.7 V to 5.5 V bus port B drivers behave much like the drivers on the PCA9515A device, while the adjustable voltage bus portA drivers drive more current and eliminate the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V LOW on the port A which accommodates smaller voltage swings of lower voltage logic.

The static offset design of the port B PCA9517A I/O drivers prevent them from being connected to another device that has rise time accelerator including the PCA9510,PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517A (port B), or PCA9518. Port A of two or more PCA9517As can be connected together, however, to allow a star topography with port A on the common bus, and port A can be connected directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517As can be connected in series, port A to port B, with nobuild-up in offset voltage with only time of flight delays to consider.

Features :

1. 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of
the device

2. Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V

3. Footprint and functional replacement for PCA9515/15A

4. I2C-bus and SMBus compatible

5. Active HIGH repeater enable input

6. Open-drain input/outputs

7. Supports arbitration and clock stretching across the repeater

8. 5V tolerant I2C-bus and enable pins

Other data sheets within the file :

PCA9517AD, PCA9517ADP, PCA9517ADP/DG, PCA9517ATP

PCA9517A Datasheet PDF Download


PCA9517A pdf