48LC16M16A2 Datasheet – 4Megx16x4banks, SDRAM – Micron

Part Number : 48LC16M16A2, MT48LC16M16A2

Function : SDR SDRAM ( 4 Meg x 16 x 4 banks )

Package : 54-ball FBGA, 54-pin TSOP II

Manufacturers : Micron Technology


48LC16M16A2 sdram micron


The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4bits. Each of the x8’s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 columns by 16 bits.


48LC16M16A2 datasheet pinout



1. PC100- and PC133-compliant

2. Fully synchronous; all signals registered on positive edge of system clock

3. Internal, pipelined operation; column address can be changed every clock cycle

4. Internal banks for hiding row access/precharge

5. Programmable burst lengths: 1, 2, 4, 8, or full page

6. Auto precharge, includes concurrent auto precharge and auto refresh modes

7. Self refresh mode (not available on AT devices)


48LC16M16A2 Datasheet PDF



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MT41J64M16LA-187 Datasheet – 8 Meg x 16, DDR3 SDRAM

Part Number : MT41J64M16LA-187

Function : 8 Meg x 16 x 8 Banks, DDR3 SDRAM

Package : 96-FBGA Package

Manufacturers : Micron Technology


MT41J64M16LA-187 datasheet sdram


The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clockcycle data transfers at the I/O pins.


1. VDD = VDDQ = +1.5V ±0.075V
2. 1.5V center-terminated push/pull I/O
3. Differential bidirectional data strobe
4. 8n-bit prefetch architecture
5. Differential clock inputs (CK, CK#)
6. 8 internal banks
7. Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals


1. Configuration
(1) 256 Meg x 4 256M4
(2) 128 Meg x 8 128M8
(3) 64 Meg x 16 64M16

4. FBGA package (Pb-free) – x4, x8
(1) 78-ball FBGA (8mm x 11.5mm) Rev. F JP
(2) 78-ball FBGA (9mm x 11.5mm) Rev. D HX
(3) 86-ball FBGA (9mm x 15.5mm) Rev. B BY

Other data sheets within the file : MT41J64M16LA-187E, MT41J64M16LA-187E:B

MT41J64M16LA-187 Datasheet PDF