ASM1442 Datasheet – TMDS level shift ICs – ASMedia

Part Number : ASM1442

Function : High speed TMDS level shift IC

Manufacturers : ASMedia Technology

Package : QFN48 Pin Type

Image :
ASM1442 image

Description :

ASM1442 is the high speed TMDS level shift ICs for High Definition Multimedia Interface (HDMI) and Digital Video Interface (DVI) video application. Those convert low-swing AC-coupled differential input from existing PCI Express in the chipset of PC to HDMI compliant differential output, supporting up to 3.4Gbps bandwidth of pixel data transition, as indicated in HDMI Rev1.3a. This conversion is automatic and transparent to the user. Only ASM1442T integrates an invertor to invert the signal of Hot Plug Detect. The devices operate at a single 3.3V supply.

Pinout

ASM1442 Datasheet

Features

1. HDMI/DVI level shifting operation up to 3.4Gbps per lane
2. Maximum data transfer rate conform with HDMI Revision 1.4a specification
3. Supporting color depths greater than 24bits deep color mode
4. Integrated 50Ω termination resistors for AC-coupled differential inputs.
5. Enable/Disable feature to turn on/off TMDS inputs and outputs to enter low-power state.
6. Output slew rate control on TMDS outputs to minimize EMI.
7. Transparent operation: no re-timing or software configuration required.
8. Integrated programmable receiving equalization.

 

ASM1442 Datasheet PDF Download

ASM1442 pdf

 

74HC595-Q100 Datasheet – 8-Bit, Shift Register

Part Number : 74HC595-Q100

Function : 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Package : SO, SSOP, TSSOP, DHVQFN 16 Pin Type

Manufacturers : NXP Semiconductors.

Pinouts :

74HC595-Q100 datasheet

 

Description :

The 74HC595-Q100, 74HCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74HC595-Q100; 74HCT595-Q100 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks. Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition ofthe storage register clock input (STCP). If both clocks are connectedtogether, the shift register is always one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features

1. Automotive product qualification in accordance with AEC-Q100 (Grade 1)
– Specified from -40 °C to +85 °C and from -40 °C to +125°C
2. 8-bit serial input
3. 8-bit serial or parallel output
4. Storage register with 3-state outputs
5. Shift register with direct clear
6. 100 MHz (typical) shift out frequency
7. ESD protection :
– MIL-STD-883, method 3015 exceeds 2000 V
– HBM JESD22-A114F exceeds 2000 V
– MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
8. Multiple package options

Applications

1. Serial-to-parallel data conversion
2. Remote control holding register

Other data sheets within the file :

74HC595BQ-Q100, 74HC595D-Q100, 74HC595DB-Q100, 74HC595PW-Q100

 

74HC595-Q100 Datasheet PDF Download


74HC595-Q100 pdf