The 74199 is a parallel in, parallel out register featuring synchronous parallel load, shift right and hold modes. State chages are initiated by the rising edge of the clock. Serial entry into the first stage is via J and K inputs for maximum flexibility. Two clock inputs are provided and it is possible to use one as an inhibit. An asychronous Mast Reset ( MR ) input overrides all other inputs and clears the register.
The 74199 is an 8−bit shift register in a 24−Lead DIP type package compatible with most other TTL and MSI logic families. All inputs are buffered to lower the drive requirements to one normalized Series 74 load, and input clamping diodes minimize switching transients to simplify system design. maximum input clock frequency is typically 35Mhz and power dissipation is typically 360mW.
Parallel loading is accomplished by applying the eight bits of data and taking the shift/load control input low when the clock input is not inhibited. The data is loaded into the associated flip−flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
1. Parallel In / Parallel Out
2. Synchronous Parallen load
3. Asynchronous overriding clear
4. JK entry to first stage
74199 Datasheet PDF
Other data sheets are available within the file: SN74199