The 74AC245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. When the output-enable (OE) is low, the device passes noninverted data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction control (DIR) input.
A high on (OE) disables the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OEshould be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
1. 2-V to 6-V VccOperation 2. Inputs Accept Voltages to 6 V 3. Max tpd of 7 ns at 5 V
74AC245 Datasheet PDF Download
Other data sheets within the file : SN74AC245, 54AC245, SN54AC245,
The LAN8710A / LAN8710Ai is a low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver with variable I/O voltage that is compliant with the IEEE 802.3-2005 standards. The LAN8710 / LAN8710Ai supports communication with an Ethernet MAC via a standard MII (IEEE 802.3u)/RMII interface. It contains a full-duplex 10-BASE-T/100BASE-TX transceiver and supports 10Mbps (10BASE-T) and 100Mbps (100BASE-TX) operation. The LAN8710A/LAN8710Ai implements auto-negotiation to automatically determine the best possible speed and duplex mode of operation. HP Auto-MDIX support allows the use of direct connect or cross-over LAN cables.
1. Single-Chip Ethernet Physical Layer Transceiver(PHY) 2. Comprehensive flexPWR®Technology (1) Flexible Power Management Architecture (2) LVCMOS Variable I/O voltage range: +1.6V to +3.6V (3) Integrated 1.2V regulator with disable feature 3. HP Auto-MDIX support 4. Small footprint 32-pin QFN lead-free RoHS compliant 5. package (5 x 5 x 0.9mm height)
Other data sheets within the file : LAN8710A-EZC-TR, LAN8710AI, LAN8710,