The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip−flop. The Set and Reset inputs are asynchronous.
1. Output Drive Capability: 10 LSTTL Loads
2. Outputs Directly Interface to CMOS, NMOS, and TTL
3. Operating Voltage Range: 2.0 to 6.0 V
4. Low Input Current: 1.0 A
5. High Noise Immunity Characteristic of CMOS Devices
6. In Compliance with the JEDEC Standard No. 7A Requirements
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at
the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Other data sheets are available within the file: 74HC74BQ, 74HC74CU, 74HC74D, 74HC74N, SN74HC74N