74LS193 Datasheet – Binary UP/Down Counter – Motorola

Part Number : 74LS193

Function : UP/DOWN MODULO-16 Binary Counter

Package : DIP, SOIC 16 Pin

Manufacturers : Motorola ( Freescale )

Pinouts :

74LS193 datasheet

Description :

TheSN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate CountUp and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs.


1. Low Power : 95 mW Typical Dissipation
2. High Speed : 40 MHz Typical Count Frequency
3. Synchronous Counting
4. Asynchronous Master Reset and Parallel Load
5. Individual Preset Inputs
6. Cascading Circuitry Internally Provided
7. Input Clamp Diodes Limit High Speed Termination Effects

Other data sheets within the file : SN74LS192, 54LS192, 54LS192J, 54LS193, 54LS193J

74LS193 Datasheet PDF Download

74LS193 pdf

74LS191 Datasheet – Synchronous 4-Bit Up/Down Counter

Part Number : 74LS191

Function : Synchronous 4-Bit Up/Down Counters With Up/Down Mode Control

Pakcage : DIP, SOP 16 Pin

Manufacturers : Texas Instruments


74LS191 Counter


Description :

The ‘190, ‘LS190, ‘191, and ‘LS191 are synchronous, reversible up/down counters having a complexity of 8 equivalent gates. The ‘191 and ‘LS191 are 4-bit binary counters and the ‘190 and ‘LS190 are BCD counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.

Pinouts :

74LS191 datasheet

The outputs of the four master-slave flip-flops are triggered on a low-to-high transition of the clock input if the enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made only when the clock input is high. The direction of the count is determined by the level of the down/up input. When low, the counter count up and when high, it counts down. A false clock may occur if the down/up input changes while the clock is low. A false ripple carry may occur if both the clock and enable are low and the down/up input is high during a load pulse.


1. Counts 8-4-2-1 BCD or Binary
2. Single Down/Up Count Control Line
3. Count Enable Control Input
4. Ripple Clock Output for Cascading
5. Asynchronously Presettable with Load Control
6. Parallel Outputs
7. Cascadable for n-Bit Applications


74LS191 Datasheet PDF Download

74LS191 pdf

Other data sheets within the file : 74190, 74191, 74LS190, 74LS191, SN54190