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74F109PC
F/fast Series Dual Positive Edge Triggered J-kbar Flip-flop Complementary Output PDIP16
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[ Descriptions ]
| 74F109 NXP Semiconductors - Positive J-K positive edge-triggered flip-flops INTEGRATED CIRCUITS 74F109 Positive J-K positive edge-triggered flip-flops Product specification IC15 Data Handbook 1990 Oct 23 Philips Semiconductors Philips Semiconductors Product specification Postive J-K positive edge-triggered flip-flops 74F109 FEATURE Industrial temperature range available ( 40°C to +85°C) DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop |
| 74F109 Fairchild Semiconductor - Dual JK Positive Edge-Triggered Flip-Flop 74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 da |
Related Information
| 74F00 Quad 2-input NAND gate - NXP Semiconductors INTEGRATED CIRCUITS 74F00 Quad 2-input NAND gate Product specification IC15 Data Handbook 1990 Oct 04 Philips Semiconductors Philips Semiconductors Product specification Quad 2-input NAND gate 74F00 FEATURE Industrial temperature range available ( 40°C to +85°C) TYPE TYPICAL PROPAGATION D |
| 74F00 Quad 2-Input NAND Gate - Fairchild Semiconductor 74F00 Quad 2-Input NAND Gate December 1994 Revised July 1999 74F00 Quad 2-Input NAND Gate General Description This device contains four independent gates, each of which performs the logic NAND function. Ordering Code: Order Number 74F00SC 74F00SJ 74F00PC Package Number M14A M14D N14A Package Desc |
Related Part Number
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