Semiconductor Informations
| 74LS32 Fairchild Semiconductor - Quad 2-Input OR Gate DM74LS32 Quad 2-Input OR Gate June 1986 Revised March 2000 DM74LS32 Quad 2-Input OR Gate General Description This device contains four independent gates each of which performs the logic OR function. Ordering Code: Order Number DM74LS32M DM74LS32SJ DM74LS32N Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small |
| 74LS32 Hitachi Semiconductor - Quadruple 2-input Positive OR Gates Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 0.05 0° 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 0.30 1.15 0° 8° + 0.20 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 |
| 74L74 Dual Positive Edge Triggered D Flip-Flop - National Semiconductor |
| 74LCX00 Low Voltage Quad 2-Input NAND Gate - Fairchild Semiconductor 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs December 2013 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs Features - 5V tolerant inputs - 2.3V 3.6V VCC specifications provided - 5.2ns tPD max. (VCC = 3.3V), 10 A ICC max. - Power down high impedance input |